Coverage for /home/runner/work/tket/tket/pytket/pytket/unit_id/__init__.py: 100%

1# Copyright Quantinuum 

2# 

3# Licensed under the Apache License, Version 2.0 (the "License"); 

4# you may not use this file except in compliance with the License. 

5# You may obtain a copy of the License at 

6# 

7# http://www.apache.org/licenses/LICENSE-2.0 

8# 

9# Unless required by applicable law or agreed to in writing, software 

10# distributed under the License is distributed on an "AS IS" BASIS, 

11# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 

12# See the License for the specific language governing permissions and 

13# limitations under the License. 

14 

15from collections.abc import Callable 

16from typing import Union 

17 

18from pytket._tket.unit_id import * 

19from pytket._tket.unit_id import ( 

20 _TEMP_BIT_NAME, 

21 _TEMP_BIT_REG_BASE, 

22 Bit, 

23 BitRegister, 

24 Qubit, 

25 QubitRegister, 

26) 

27from pytket.circuit.logic_exp import ( 

28 BitLogicExp, 

29 BitWiseOp, 

30 Constant, 

31 LogicExp, 

32 RegLogicExp, 

33 RegWiseOp, 

34 create_bit_logic_exp, 

35 create_reg_logic_exp, 

36) 

37 

38 

39def _bitregister_next(self: BitRegister) -> Bit: 

40 if self._current < self.size: 

41 result = self[self._current] 

42 self._current += 1 

43 return result 

44 raise StopIteration 

45 

46 

47def _qubitregister_next(self: QubitRegister) -> Qubit: 

48 if self._current < self.size: 

49 result = self[self._current] 

50 self._current += 1 

51 return result 

52 raise StopIteration 

53 

54 

55setattr(BitRegister, "__next__", _bitregister_next) # noqa: B010 

56BitRegister.__next__.__name__ = "__next__" 

57 

58setattr(QubitRegister, "__next__", _qubitregister_next) # noqa: B010 

59QubitRegister.__next__.__name__ = "__next__" 

60 

61# overload operators for Bit, BitRegister and expressions over these 

62# such that the operation returns a LogicExp describing the operation 

63 

64BitArgType = Union[LogicExp, Bit, Constant] # noqa: UP007 

65RegArgType = Union[LogicExp, BitRegister, Constant] # noqa: UP007 

66 

67 

68def _gen_binary_method_bit( 

69 op: BitWiseOp, name: str 

70) -> Callable[[BitArgType, BitArgType], BitLogicExp]: 

71 def logic_operation(self: BitArgType, other: BitArgType) -> BitLogicExp: 

72 return create_bit_logic_exp(op, [self, other]) 

73 

74 logic_operation.__name__ = name 

75 return logic_operation 

76 

77 

78def _gen_binary_method_reg( 

79 op: RegWiseOp, name: str 

80) -> Callable[[RegArgType, RegArgType], RegLogicExp]: 

81 def logic_operation(self: RegArgType, other: RegArgType) -> RegLogicExp: 

82 return create_reg_logic_exp(op, [self, other]) 

83 

84 logic_operation.__name__ = name 

85 return logic_operation 

86 

87 

88setattr(Bit, "__and__", _gen_binary_method_bit(BitWiseOp.AND, "__and__")) # noqa: B010 

89setattr(Bit, "__rand__", _gen_binary_method_bit(BitWiseOp.AND, "__rand__")) # noqa: B010 

90setattr(Bit, "__or__", _gen_binary_method_bit(BitWiseOp.OR, "__or__")) # noqa: B010 

91setattr(Bit, "__ror__", _gen_binary_method_bit(BitWiseOp.OR, "__ror__")) # noqa: B010 

92setattr(Bit, "__xor__", _gen_binary_method_bit(BitWiseOp.XOR, "__xor__")) # noqa: B010 

93setattr(Bit, "__rxor__", _gen_binary_method_bit(BitWiseOp.XOR, "__rxor__")) # noqa: B010 

94setattr(BitRegister, "__and__", _gen_binary_method_reg(RegWiseOp.AND, "__and__")) # noqa: B010 

95setattr(BitRegister, "__rand__", _gen_binary_method_reg(RegWiseOp.AND, "__rand__")) # noqa: B010 

96setattr(BitRegister, "__or__", _gen_binary_method_reg(RegWiseOp.OR, "__or__")) # noqa: B010 

97setattr(BitRegister, "__ror__", _gen_binary_method_reg(RegWiseOp.OR, "__ror__")) # noqa: B010 

98setattr(BitRegister, "__xor__", _gen_binary_method_reg(RegWiseOp.XOR, "__xor__")) # noqa: B010 

99setattr(BitRegister, "__rxor__", _gen_binary_method_reg(RegWiseOp.XOR, "__rxor__")) # noqa: B010 

100setattr(BitRegister, "__add__", _gen_binary_method_reg(RegWiseOp.ADD, "__add__")) # noqa: B010 

101setattr(BitRegister, "__sub__", _gen_binary_method_reg(RegWiseOp.SUB, "__sub__")) # noqa: B010 

102setattr(BitRegister, "__mul__", _gen_binary_method_reg(RegWiseOp.MUL, "__mul__")) # noqa: B010 

103setattr( # noqa: B010 

104 BitRegister, "__floordiv__", _gen_binary_method_reg(RegWiseOp.DIV, "__floordiv__") 

105) 

106setattr(BitRegister, "__pow__", _gen_binary_method_reg(RegWiseOp.POW, "__pow__")) # noqa: B010 

107setattr(BitRegister, "__lshift__", _gen_binary_method_reg(RegWiseOp.LSH, "__lshift__")) # noqa: B010 

108setattr(BitRegister, "__rshift__", _gen_binary_method_reg(RegWiseOp.RSH, "__rshift__")) # noqa: B010