Coverage for /home/runner/work/tket/tket/pytket/pytket/unit_id/__init__.py: 100%

1# Copyright Quantinuum 

2# 

3# Licensed under the Apache License, Version 2.0 (the "License"); 

4# you may not use this file except in compliance with the License. 

5# You may obtain a copy of the License at 

6# 

7# http://www.apache.org/licenses/LICENSE-2.0 

8# 

9# Unless required by applicable law or agreed to in writing, software 

10# distributed under the License is distributed on an "AS IS" BASIS, 

11# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 

12# See the License for the specific language governing permissions and 

13# limitations under the License. 

14 

15from typing import Callable, Union 

16 

17from pytket._tket.unit_id import * 

18from pytket._tket.unit_id import ( 

19 _TEMP_BIT_NAME, 

20 _TEMP_BIT_REG_BASE, 

21 Bit, 

22 BitRegister, 

23 Qubit, 

24 QubitRegister, 

25) 

26from pytket.circuit.logic_exp import ( 

27 BitLogicExp, 

28 BitWiseOp, 

29 Constant, 

30 LogicExp, 

31 RegLogicExp, 

32 RegWiseOp, 

33 create_bit_logic_exp, 

34 create_reg_logic_exp, 

35) 

36 

37 

38def _bitregister_next(self: BitRegister) -> Bit: 

39 if self._current < self.size: 

40 result = self[self._current] 

41 self._current += 1 

42 return result 

43 raise StopIteration 

44 

45 

46def _qubitregister_next(self: QubitRegister) -> Qubit: 

47 if self._current < self.size: 

48 result = self[self._current] 

49 self._current += 1 

50 return result 

51 raise StopIteration 

52 

53 

54setattr(BitRegister, "__next__", _bitregister_next) 

55BitRegister.__next__.__name__ = "__next__" 

56 

57setattr(QubitRegister, "__next__", _qubitregister_next) 

58QubitRegister.__next__.__name__ = "__next__" 

59 

60# overload operators for Bit, BitRegister and expressions over these 

61# such that the operation returns a LogicExp describing the operation 

62 

63BitArgType = Union[LogicExp, Bit, Constant] 

64RegArgType = Union[LogicExp, BitRegister, Constant] 

65 

66 

67def gen_binary_method_bit( 

68 op: BitWiseOp, name: str 

69) -> Callable[[BitArgType, BitArgType], BitLogicExp]: 

70 def logic_operation(self: BitArgType, other: BitArgType) -> BitLogicExp: 

71 return create_bit_logic_exp(op, [self, other]) 

72 

73 logic_operation.__name__ = name 

74 return logic_operation 

75 

76 

77def gen_binary_method_reg( 

78 op: RegWiseOp, name: str 

79) -> Callable[[RegArgType, RegArgType], RegLogicExp]: 

80 def logic_operation(self: RegArgType, other: RegArgType) -> RegLogicExp: 

81 return create_reg_logic_exp(op, [self, other]) 

82 

83 logic_operation.__name__ = name 

84 return logic_operation 

85 

86 

87setattr(Bit, "__and__", gen_binary_method_bit(BitWiseOp.AND, "__and__")) 

88setattr(Bit, "__rand__", gen_binary_method_bit(BitWiseOp.AND, "__rand__")) 

89setattr(Bit, "__or__", gen_binary_method_bit(BitWiseOp.OR, "__or__")) 

90setattr(Bit, "__ror__", gen_binary_method_bit(BitWiseOp.OR, "__ror__")) 

91setattr(Bit, "__xor__", gen_binary_method_bit(BitWiseOp.XOR, "__xor__")) 

92setattr(Bit, "__rxor__", gen_binary_method_bit(BitWiseOp.XOR, "__rxor__")) 

93setattr(BitRegister, "__and__", gen_binary_method_reg(RegWiseOp.AND, "__and__")) 

94setattr(BitRegister, "__rand__", gen_binary_method_reg(RegWiseOp.AND, "__rand__")) 

95setattr(BitRegister, "__or__", gen_binary_method_reg(RegWiseOp.OR, "__or__")) 

96setattr(BitRegister, "__ror__", gen_binary_method_reg(RegWiseOp.OR, "__ror__")) 

97setattr(BitRegister, "__xor__", gen_binary_method_reg(RegWiseOp.XOR, "__xor__")) 

98setattr(BitRegister, "__rxor__", gen_binary_method_reg(RegWiseOp.XOR, "__rxor__")) 

99setattr(BitRegister, "__add__", gen_binary_method_reg(RegWiseOp.ADD, "__add__")) 

100setattr(BitRegister, "__sub__", gen_binary_method_reg(RegWiseOp.SUB, "__sub__")) 

101setattr(BitRegister, "__mul__", gen_binary_method_reg(RegWiseOp.MUL, "__mul__")) 

102setattr( 

103 BitRegister, "__floordiv__", gen_binary_method_reg(RegWiseOp.DIV, "__floordiv__") 

104) 

105setattr(BitRegister, "__pow__", gen_binary_method_reg(RegWiseOp.POW, "__pow__")) 

106setattr(BitRegister, "__lshift__", gen_binary_method_reg(RegWiseOp.LSH, "__lshift__")) 

107setattr(BitRegister, "__rshift__", gen_binary_method_reg(RegWiseOp.RSH, "__rshift__"))