GCC Code Coverage Report

Directory: ./
File: Converters/ZXConverters.cpp
Date: 2022-10-15 05:10:18
Warnings: 11 unchecked decisions!
Exec Total Coverage
Lines: 567 622 91.2%
Functions: 12 12 100.0%
Branches: 649 1335 48.6%
Decisions: 121 167 72.5%
Line Branch Decision Exec Source
1 // Copyright 2019-2022 Cambridge Quantum Computing
2 //
3 // Licensed under the Apache License, Version 2.0 (the "License");
4 // you may not use this file except in compliance with the License.
5 // You may obtain a copy of the License at
6 //
7 // http://www.apache.org/licenses/LICENSE-2.0
8 //
9 // Unless required by applicable law or agreed to in writing, software
10 // distributed under the License is distributed on an "AS IS" BASIS,
11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12 // See the License for the specific language governing permissions and
13 // limitations under the License.
14
15 #include "Circuit/CircPool.hpp"
16 #include "Converters.hpp"
17 #include "ZX/Flow.hpp"
18 #include "ZX/ZXDiagram.hpp"
19
20 namespace tket {
21
22 using namespace zx;
23
24 enum class ZXPortType { In, Out };
25 typedef std::pair<VertPort, ZXPortType> TypedVertPort;
26 typedef std::pair<ZXVert, std::optional<unsigned>> ZXVertPort;
27 typedef std::vector<ZXVertPort> ZXVertPortVec;
28 typedef boost::bimap<ZXVert, Vertex> BoundaryVertMap;
29
30 366 bool is_spiderless_optype(const OpType& optype) {
31
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 680 return optype == OpType::Barrier || optype == OpType::SWAP ||
32
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 680 optype == OpType::noop;
33 }
34
35 // Add a swicth with the on-state controlled by the on_value.
36 // qtype indicates the quantum type of the switch.
37 32 std::pair<ZXVertPort, ZXVertPort> add_switch(
38 ZXDiagram& zxd, const bool& on_value, const QuantumType& qtype) {
39
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 32 zxd.multiply_scalar(std::sqrt(2.));
40
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 32 ZXVert triangle = zxd.add_vertex(ZXType::Triangle, qtype);
41
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 32 ZXVert x = zxd.add_vertex(ZXType::XSpider, 0, qtype);
42
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 32 zxd.add_wire(triangle, x, ZXWireType::Basic, qtype, 1);
43
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 32 if (on_value) {
44 // Turn on the switch if the input is 1
45
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 16 ZXVert negate = zxd.add_vertex(ZXType::XSpider, 1, qtype);
46
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 16 zxd.add_wire(triangle, negate, ZXWireType::Basic, qtype, 0);
47 16 return {{negate, std::nullopt}, {x, std::nullopt}};
48 }
49 16 return {{triangle, 0}, {x, std::nullopt}};
50 }
51
52 // --o--s---o--
53 // | |
54 // n n
55 // |--G-o-|
56 // |
57 // s
58 // |-discard
59 // s, n are switches, G is the conditional zx diagram specified by 'left' and
60 // 'right'. s is on when the input is 0, n is on when the input is 1.
61 // return the input and the output of the conditional zx along with a vector of
62 // control spiders
63 8 std::pair<std::pair<ZXVertPort, ZXVertPort>, ZXVertPortVec> add_conditional_zx(
64 ZXDiagram& zxd, const ZXVert& left, const ZXVert& right,
65 const QuantumType& qtype) {
66
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 8 ZXVert in = zxd.add_vertex(ZXType::ZSpider, 0, qtype);
67
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 8 ZXVert out = zxd.add_vertex(ZXType::ZSpider, 0, qtype);
68
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 8 ZXVert discard_ctr = zxd.add_vertex(ZXType::ZSpider, 0, qtype);
69
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 8 ZXVert discard = zxd.add_vertex(ZXType::ZSpider, 0, QuantumType::Classical);
70
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 8 auto switch_s0 = add_switch(zxd, false, qtype);
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 8 auto switch_n0 = add_switch(zxd, true, qtype);
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 8 auto switch_n1 = add_switch(zxd, true, qtype);
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 8 auto switch_s1 = add_switch(zxd, false, qtype);
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 8 zxd.add_wire(in, switch_s0.second.first, ZXWireType::Basic, qtype);
75
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 8 zxd.add_wire(out, switch_s0.second.first, ZXWireType::Basic, qtype);
76
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 8 zxd.add_wire(in, switch_n0.second.first, ZXWireType::Basic, qtype);
77
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 8 zxd.add_wire(left, switch_n0.second.first, ZXWireType::Basic, qtype);
78
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 8 zxd.add_wire(right, discard_ctr, ZXWireType::Basic, qtype);
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 8 zxd.add_wire(discard_ctr, switch_n1.second.first, ZXWireType::Basic, qtype);
80
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 8 zxd.add_wire(out, switch_n1.second.first, ZXWireType::Basic, qtype);
81
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 8 zxd.add_wire(discard_ctr, switch_s1.second.first, ZXWireType::Basic, qtype);
82
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 8 zxd.add_wire(discard, switch_s1.second.first, ZXWireType::Basic, qtype);
83 return {
84 {{in, std::nullopt}, {out, std::nullopt}},
85
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 8 {switch_s0.first, switch_s1.first, switch_n0.first, switch_n1.first}};
86 }
87
88 // n-bit AND spider to control the switches
89 // https://arxiv.org/abs/1910.06818
90 2 std::pair<ZXVertPortVec, ZXVertPort> add_n_bit_and(
91 ZXDiagram& zxd, unsigned n, const QuantumType& qtype) {
92 TKET_ASSERT(n > 1);
93
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 2 ZXVert z_vert = zxd.add_vertex(ZXType::ZSpider, 0, qtype);
94 // Add Triangle -1
95
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 2 ZXVert z_pi_0 = zxd.add_vertex(ZXType::ZSpider, 1, qtype);
96
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 2 ZXVert tri_1 = zxd.add_vertex(ZXType::Triangle, qtype);
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 2 ZXVert z_pi_1 = zxd.add_vertex(ZXType::ZSpider, 1, qtype);
98
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 2 zxd.add_wire(z_vert, z_pi_0, ZXWireType::Basic, qtype);
99
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 2 zxd.add_wire(tri_1, z_pi_0, ZXWireType::Basic, qtype, 0);
100
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 2 zxd.add_wire(tri_1, z_pi_1, ZXWireType::Basic, qtype, 1);
101 2 ZXVertPortVec inputs;
102
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 7 for (unsigned i = 0; i < n; i++) {
103
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 5 ZXVert tri_0 = zxd.add_vertex(ZXType::Triangle, qtype);
104
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 5 zxd.add_wire(tri_0, z_vert, ZXWireType::Basic, qtype, 1);
105
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 5 inputs.push_back({tri_0, 0});
106 }
107
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 4 return {inputs, {z_pi_1, std::nullopt}};
108 2 }
109
110 // Add converted circ into zxd. Set add_boundary to true
111 // if boundary spiders are to be added to the boundary.
112 38 BoundaryVertMap circuit_to_zx_recursive(
113 const Circuit& circ, ZXDiagram& zxd, bool add_boundary) {
114 38 std::map<TypedVertPort, ZXVertPort> vert_lookup;
115 38 std::map<VertPort, ZXVertPort> boolean_outport_lookup;
116
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 38 BoundaryVertMap bmap;
117
118 // Convert each vertex to ZXDiagram, raise error if not supported
119
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 296 BGL_FORALL_VERTICES(vert, circ.dag, DAG) {
120 // We currently throw an error if the vertex is either classical or flow
121
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 221 Op_ptr op = circ.get_Op_ptr_from_Vertex(vert);
122
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 221 if (is_flowop_type(op->get_type()) || is_classical_type(op->get_type())) {
123 ✗ throw Unsupported(
124 ✗ "Cannot convert OpType: " + op->get_name() + " to a ZX node. \n");
125 }
126
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 221 switch (op->get_type()) {
127
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 62 case OpType::Input: {
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 62 ZXVert zx_vert = zxd.add_vertex(ZXType::Input, QuantumType::Quantum);
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 62 if (add_boundary) zxd.add_boundary(zx_vert);
130
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 62 vert_lookup.insert(
131 62 {{{vert, 0}, ZXPortType::Out}, {zx_vert, std::nullopt}});
132
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 62 bmap.insert({zx_vert, vert});
133 62 break;
134 }
135
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 62 case OpType::Output: {
136
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 62 ZXVert zx_vert = zxd.add_vertex(ZXType::Output, QuantumType::Quantum);
137
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 62 if (add_boundary) zxd.add_boundary(zx_vert);
138
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 62 vert_lookup.insert(
139 62 {{{vert, 0}, ZXPortType::In}, {zx_vert, std::nullopt}});
140
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 62 bmap.insert({zx_vert, vert});
141 62 break;
142 }
143
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 15 case OpType::ClInput: {
144
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 15 ZXVert zx_vert = zxd.add_vertex(ZXType::Input, QuantumType::Classical);
145
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 15 if (add_boundary) zxd.add_boundary(zx_vert);
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 15 vert_lookup.insert(
147 15 {{{vert, 0}, ZXPortType::Out}, {zx_vert, std::nullopt}});
148
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 15 bmap.insert({zx_vert, vert});
149 15 break;
150 }
151
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 15 case OpType::ClOutput: {
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 15 ZXVert zx_vert = zxd.add_vertex(ZXType::Output, QuantumType::Classical);
153
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 15 if (add_boundary) zxd.add_boundary(zx_vert);
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 15 vert_lookup.insert(
155 15 {{{vert, 0}, ZXPortType::In}, {zx_vert, std::nullopt}});
156
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 15 bmap.insert({zx_vert, vert});
157 15 break;
158 }
159 // Spiderless ops are handled during vertex wiring
160 17 case OpType::Barrier:
161 case OpType::noop:
162 case OpType::SWAP: {
163 17 continue;
164 }
165
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 9 case OpType::H: {
166
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 9 ZXVert zx_vert = zxd.add_vertex(ZXType::Hbox, QuantumType::Quantum);
167
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 9 vert_lookup.insert(
168 9 {{{vert, 0}, ZXPortType::In}, {zx_vert, std::nullopt}});
169
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 9 vert_lookup.insert(
170 9 {{{vert, 0}, ZXPortType::Out}, {zx_vert, std::nullopt}});
171
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 9 zxd.multiply_scalar(0.5);
172 9 break;
173 }
174
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 7 case OpType::Rz: {
175
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 7 ZXVert zx_vert = zxd.add_vertex(
176
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 14 ZXType::ZSpider, op->get_params()[0], QuantumType::Quantum);
177
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 7 vert_lookup.insert(
178 7 {{{vert, 0}, ZXPortType::In}, {zx_vert, std::nullopt}});
179
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 7 vert_lookup.insert(
180 7 {{{vert, 0}, ZXPortType::Out}, {zx_vert, std::nullopt}});
181 7 break;
182 }
183
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 2 case OpType::Rx: {
184
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 2 ZXVert zx_vert = zxd.add_vertex(
185
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 4 ZXType::XSpider, op->get_params()[0], QuantumType::Quantum);
186
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 2 vert_lookup.insert(
187 2 {{{vert, 0}, ZXPortType::In}, {zx_vert, std::nullopt}});
188
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 2 vert_lookup.insert(
189 2 {{{vert, 0}, ZXPortType::Out}, {zx_vert, std::nullopt}});
190 2 break;
191 }
192 5 case OpType::X: {
193 ZXVert zx_vert =
194
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 5 zxd.add_vertex(ZXType::XSpider, 1, QuantumType::Quantum);
195
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 5 vert_lookup.insert(
196 5 {{{vert, 0}, ZXPortType::In}, {zx_vert, std::nullopt}});
197
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 5 vert_lookup.insert(
198 5 {{{vert, 0}, ZXPortType::Out}, {zx_vert, std::nullopt}});
199 5 break;
200 }
201 1 case OpType::Z: {
202 ZXVert zx_vert =
203
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 1 zxd.add_vertex(ZXType::ZSpider, 1, QuantumType::Quantum);
204
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 1 vert_lookup.insert(
205 1 {{{vert, 0}, ZXPortType::In}, {zx_vert, std::nullopt}});
206
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 1 vert_lookup.insert(
207 1 {{{vert, 0}, ZXPortType::Out}, {zx_vert, std::nullopt}});
208 1 break;
209 }
210 4 case OpType::CX: {
211 ZXVert zx_x_vert =
212
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 4 zxd.add_vertex(ZXType::XSpider, 0, QuantumType::Quantum);
213 ZXVert zx_z_vert =
214
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 4 zxd.add_vertex(ZXType::ZSpider, 0, QuantumType::Quantum);
215
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 4 zxd.add_wire(zx_x_vert, zx_z_vert);
216
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 4 vert_lookup.insert(
217 4 {{{vert, 0}, ZXPortType::In}, {zx_z_vert, std::nullopt}});
218
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 4 vert_lookup.insert(
219 4 {{{vert, 0}, ZXPortType::Out}, {zx_z_vert, std::nullopt}});
220
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 4 vert_lookup.insert(
221 4 {{{vert, 1}, ZXPortType::In}, {zx_x_vert, std::nullopt}});
222
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 4 vert_lookup.insert(
223 4 {{{vert, 1}, ZXPortType::Out}, {zx_x_vert, std::nullopt}});
224
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 4 zxd.multiply_scalar(2);
225 4 break;
226 }
227 3 case OpType::CZ: {
228 ZXVert zx_za_vert =
229
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 3 zxd.add_vertex(ZXType::ZSpider, 0, QuantumType::Quantum);
230 ZXVert zx_zb_vert =
231
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 3 zxd.add_vertex(ZXType::ZSpider, 0, QuantumType::Quantum);
232
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 3 zxd.add_wire(zx_za_vert, zx_zb_vert, ZXWireType::H);
233
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 3 vert_lookup.insert(
234 3 {{{vert, 0}, ZXPortType::In}, {zx_za_vert, std::nullopt}});
235
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 3 vert_lookup.insert(
236 3 {{{vert, 0}, ZXPortType::Out}, {zx_za_vert, std::nullopt}});
237
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 3 vert_lookup.insert(
238 3 {{{vert, 1}, ZXPortType::In}, {zx_zb_vert, std::nullopt}});
239
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 3 vert_lookup.insert(
240 3 {{{vert, 1}, ZXPortType::Out}, {zx_zb_vert, std::nullopt}});
241 3 break;
242 }
243
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 4 case OpType::Measure: {
244 // Add a decoherence node
245 ZXVert zx_measure_vert =
246
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 4 zxd.add_vertex(ZXType::ZSpider, 0, QuantumType::Classical);
247 // Add a delete operator
248 ZXVert zx_delete_vert =
249
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 4 zxd.add_vertex(ZXType::ZSpider, 0, QuantumType::Classical);
250
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 4 vert_lookup.insert(
251 4 {{{vert, 0}, ZXPortType::In}, {zx_measure_vert, std::nullopt}});
252
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 4 vert_lookup.insert(
253 4 {{{vert, 0}, ZXPortType::Out}, {zx_measure_vert, std::nullopt}});
254
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 4 vert_lookup.insert(
255 4 {{{vert, 1}, ZXPortType::In}, {zx_delete_vert, std::nullopt}});
256
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 4 vert_lookup.insert(
257 4 {{{vert, 1}, ZXPortType::Out}, {zx_measure_vert, std::nullopt}});
258 4 break;
259 }
260
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 2 case OpType::Reset: {
261 // Discard
262 ZXVert zx_discard_vert =
263
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 2 zxd.add_vertex(ZXType::ZSpider, 0, QuantumType::Classical);
264 // Add a node to prepare |0>
265 ZXVert zx_reset_vert =
266
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 2 zxd.add_vertex(ZXType::XSpider, 0, QuantumType::Quantum);
267
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 2 zxd.multiply_scalar(0.5);
268
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 2 vert_lookup.insert(
269 2 {{{vert, 0}, ZXPortType::In}, {zx_discard_vert, std::nullopt}});
270
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 2 vert_lookup.insert(
271 2 {{{vert, 0}, ZXPortType::Out}, {zx_reset_vert, std::nullopt}});
272 2 break;
273 }
274 2 case OpType::Collapse: {
275 ZXVert zx_vert =
276
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 2 zxd.add_vertex(ZXType::ZSpider, QuantumType::Classical);
277
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 2 vert_lookup.insert(
278 2 {{{vert, 0}, ZXPortType::In}, {zx_vert, std::nullopt}});
279
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 2 vert_lookup.insert(
280 2 {{{vert, 0}, ZXPortType::Out}, {zx_vert, std::nullopt}});
281 2 break;
282 }
283 1 case OpType::Create: {
284 ZXVert zx_init_vert =
285
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 1 zxd.add_vertex(ZXType::XSpider, 0, QuantumType::Quantum);
286
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 1 zxd.multiply_scalar(0.5);
287
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 1 vert_lookup.insert(
288 1 {{{vert, 0}, ZXPortType::Out}, {zx_init_vert, std::nullopt}});
289 1 break;
290 }
291 1 case OpType::Discard: {
292 ZXVert zx_discard_vert =
293
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 1 zxd.add_vertex(ZXType::ZSpider, 0, QuantumType::Classical);
294
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 1 vert_lookup.insert(
295 1 {{{vert, 0}, ZXPortType::In}, {zx_discard_vert, std::nullopt}});
296 1 break;
297 }
298
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 6 case OpType::Conditional: {
299 // Stores the condition for each port index
300 6 std::vector<bool> port_conditions;
301
302
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 6 op_signature_t parent_sig = op->get_signature();
303
304 // Find the nested quantum op and its overall conditions
305 // Assume bool ports are always the first few ports
306
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 13 while (op->get_type() == OpType::Conditional) {
307 7 const Conditional& cond = static_cast<const Conditional&>(*op);
308
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 16 for (unsigned i = 0; i < cond.get_width(); i++) {
309
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 9 bool set = cond.get_value() & (1 << (cond.get_width() - i - 1));
310
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 9 port_conditions.push_back(set);
311 }
312
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 7 op = cond.get_op();
313 }
314 unsigned port_conditions_size =
315 6 static_cast<unsigned>(port_conditions.size());
316 // Convert the underlying op to zx.
317 // If the op is a quantum gate, construct a 1 gate circuit
318 // If the op is a box, obtain its circuit decomposition
319
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 6 op_signature_t inner_sig = op->get_signature();
320
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 6 Circuit replacement;
321
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 6 if (is_box_type(op->get_type())) {
322 1 const Box& b = static_cast<const Box&>(*op);
323
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 1 replacement = *b.to_circuit();
324 } else {
325 5 unit_vector_t args;
326 5 unsigned q_index = 0;
327 5 unsigned c_index = 0;
328
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 11 for (const EdgeType& etype : inner_sig) {
329
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 6 if (etype == EdgeType::Quantum) {
330
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 5 args.push_back(Qubit(q_index++));
331
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 1 } else if (etype == EdgeType::Classical) {
332
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 1 args.push_back(Bit(c_index++));
333 }
334 TKET_ASSERT(etype != EdgeType::Boolean);
335 }
336
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 5 replacement = Circuit(q_index, c_index);
337
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 5 replacement.add_op(op, args);
338 5 }
339 BoundaryVertMap box_bm =
340
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 6 circuit_to_zx_recursive(replacement, zxd, false);
341
342 // The Z spider controlling all switches
343 ZXVert master_switch =
344
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 6 zxd.add_vertex(ZXType::ZSpider, 0, QuantumType::Classical);
345
346 // For each qubit/bit path in the inner op, convert it into a
347 // conditional path.
348 6 unsigned q_index = 0;
349 6 unsigned c_index = 0;
350
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 14 for (unsigned i = 0; i < inner_sig.size(); i++) {
351 QuantumType qtype;
352
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 8 UnitID reg;
353
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 8 if (inner_sig[i] == EdgeType::Quantum) {
354 7 qtype = QuantumType::Quantum;
355
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 7 reg = Qubit(q_index++);
356 } else {
357 1 qtype = QuantumType::Classical;
358
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 1 reg = Bit(c_index++);
359 }
360 8 std::pair<ZXVertPort, ZXVertPort> boundary;
361 8 ZXVertPortVec controls;
362
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 8 Vertex inp = replacement.get_in(reg);
363
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 8 ZXVert zx_inp = box_bm.right.at(inp);
364
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 8 Vertex outp = replacement.get_out(reg);
365
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 8 ZXVert zx_outp = box_bm.right.at(outp);
366 // Convert the path between zx_inp and zx_outp into a conditional
367 // path
368 8 std::tie(boundary, controls) =
369
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 16 add_conditional_zx(zxd, zx_inp, zx_outp, qtype);
370 // Connect each switch to the master switch
371
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 40 for (const ZXVertPort& ctr : controls) {
372 32 zxd.add_wire(
373 32 ctr.first, master_switch, ZXWireType::Basic,
374
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 32 zxd.get_qtype(ctr.first).value(), ctr.second);
375 }
376 // Update lookup
377 TKET_ASSERT(parent_sig[i + port_conditions_size] == inner_sig[i]);
378 // Since we assume that the conditions always use the first few
379 // ports, the gate path should use the i + port_conditions.size()
380 // port.
381
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 8 vert_lookup.insert(
382 8 {{{vert, i + port_conditions_size}, ZXPortType::In},
383 boundary.first});
384
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 8 vert_lookup.insert(
385 8 {{{vert, i + port_conditions_size}, ZXPortType::Out},
386 boundary.second});
387 8 }
388 // Use either a Z spider or a AND operator to connect the master
389 // switch and the boolean inputs
390 6 ZXVertPortVec and_inputs;
391
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 6 if (port_conditions_size == 1) {
392
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 4 and_inputs.push_back({master_switch, std::nullopt});
393 } else {
394 2 ZXVertPort and_output;
395 2 std::tie(and_inputs, and_output) =
396
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 4 add_n_bit_and(zxd, port_conditions_size, QuantumType::Classical);
397
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 2 zxd.add_wire(
398 and_output.first, master_switch, ZXWireType::Basic,
399 QuantumType::Classical, and_output.second);
400 }
401 // Connect inputs to the nodes obtained from above
402
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 15 for (unsigned i = 0; i < port_conditions_size; i++) {
403 // Each boolean edge shares a source port with other
404 // classical/boolean edges. Use the classical Z spider to explicitly
405 // implement this copy operation
406
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 9 Edge in_edge = circ.get_nth_in_edge(vert, i);
407
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 9 port_t source_port = circ.get_source_port(in_edge);
408
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 9 Vertex vert_s = circ.source(in_edge);
409 // During the wiring stage, each edge originated from {vert_s,
410 // p_s} needs go through copy_vert
411
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 9 if (boolean_outport_lookup.find({vert_s, source_port}) ==
412
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 18 boolean_outport_lookup.end()) {
413 ZXVert copy_vert =
414
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 8 zxd.add_vertex(ZXType::ZSpider, 0, QuantumType::Classical);
415
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 8 boolean_outport_lookup.insert(
416 {{vert_s, source_port}, {copy_vert, std::nullopt}});
417 }
418
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 9 if (port_conditions[i]) {
419
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 7 vert_lookup.insert({{{vert, i}, ZXPortType::In}, and_inputs[i]});
420 } else {
421 ZXVert x_vert =
422
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 2 zxd.add_vertex(ZXType::XSpider, 1, QuantumType::Classical);
423 2 zxd.add_wire(
424
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 2 and_inputs[i].first, x_vert, ZXWireType::Basic,
425 2 QuantumType::Classical, and_inputs[i].second);
426
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 4 vert_lookup.insert(
427 4 {{{vert, i}, ZXPortType::In}, {x_vert, std::nullopt}});
428 }
429 }
430 6 break;
431 6 }
432
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 3 default:
433
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 3 if (is_box_type(op->get_type())) {
434 EdgeVec b_in_holes =
435
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 3 circ.get_in_edges_of_type(vert, EdgeType::Boolean);
436
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 3 if (b_in_holes.size() > 0) {
437 ✗ throw Unsupported("Cannot convert box type: " + op->get_name());
438 }
439 3 const Box& b = static_cast<const Box&>(*op);
440
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 3 Circuit replacement = *b.to_circuit();
441 // First, add the converted box to diagram.
442 BoundaryVertMap box_bm =
443
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 3 circuit_to_zx_recursive(replacement, zxd, false);
444 // Then, map the vertports in the box boundary to zx nodes.
445 // Assume that a box can't have Boolean input edges, and all Boolean
446 // output edges share ports with Classical edges. Therefore we don't
447 // have to map Boolean vertports.
448 EdgeVec q_in_holes =
449
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 3 circ.get_in_edges_of_type(vert, EdgeType::Quantum);
450 EdgeVec q_out_holes =
451
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 3 circ.get_out_edges_of_type(vert, EdgeType::Quantum);
452 EdgeVec c_in_holes =
453
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 3 circ.get_in_edges_of_type(vert, EdgeType::Classical);
454 EdgeVec c_out_holes =
455
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 3 circ.get_out_edges_of_type(vert, EdgeType::Classical);
456
457
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 11 for (unsigned i = 0; i < q_in_holes.size(); i++) {
458
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 8 port_t port = circ.get_target_port(q_in_holes[i]);
459
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 8 Vertex inp = replacement.get_in(Qubit(i));
460
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 16 vert_lookup.insert(
461 16 {{{vert, port}, ZXPortType::In},
462
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 8 {box_bm.right.at(inp), std::nullopt}});
463 }
464
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 11 for (unsigned i = 0; i < q_out_holes.size(); i++) {
465
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 8 port_t port = circ.get_source_port(q_out_holes[i]);
466
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 8 Vertex outp = replacement.get_out(Qubit(i));
467
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 16 vert_lookup.insert(
468 16 {{{vert, port}, ZXPortType::Out},
469
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 8 {box_bm.right.at(outp), std::nullopt}});
470 }
471
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 3 for (unsigned i = 0; i < c_in_holes.size(); i++) {
472 ✗ port_t port = circ.get_target_port(c_in_holes[i]);
473 ✗ Vertex inp = replacement.get_in(Bit(i));
474 ✗ vert_lookup.insert(
475 ✗ {{{vert, port}, ZXPortType::In},
476 ✗ {box_bm.right.at(inp), std::nullopt}});
477 }
478
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 3 for (unsigned i = 0; i < c_out_holes.size(); i++) {
479 ✗ port_t port = circ.get_source_port(c_out_holes[i]);
480 ✗ Vertex outp = replacement.get_out(Bit(i));
481 ✗ vert_lookup.insert(
482 ✗ {{{vert, port}, ZXPortType::Out},
483 ✗ {box_bm.right.at(outp), std::nullopt}});
484 }
485 3 } else {
486 ✗ throw Unsupported(
487 ✗ "Cannot convert gate type: " + op->get_name() +
488 " to a ZX node, try rebase the gates to use Rx, Rz, "
489 "X, Z, H, CZ "
490 ✗ "or CX. \n");
491 }
492 17 }
493
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 221 }
494
495 // Connect the ZX nodes
496
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 258 BGL_FORALL_EDGES(edge, circ.dag, DAG) {
497
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 183 Vertex v_s = circ.source(edge);
498
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 183 Vertex v_t = circ.target(edge);
499
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 183 port_t p_s = circ.get_source_port(edge);
500
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 183 port_t p_t = circ.get_target_port(edge);
501 // Handle Spiderless ops
502
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 183 if (is_spiderless_optype(circ.get_OpType_from_Vertex(v_s))) {
503 // We only handle in-edges
504 30 continue;
505 }
506
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 153 if (is_spiderless_optype(circ.get_OpType_from_Vertex(v_t))) {
507 // Traverse the path to find the next non-spiderless op
508 15 Edge next_e = edge;
509 do {
510
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 30 if (circ.get_OpType_from_Vertex(v_t) == OpType::SWAP) {
511 12 next_e = circ.get_nth_out_edge(
512
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 12 v_t, (circ.get_target_port(next_e) + 1) % 2);
513
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 12 v_t = circ.target(next_e);
514 } else {
515
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 18 std::tie(v_t, next_e) = circ.get_next_pair(v_t, next_e);
516 }
517
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 30 } while (is_spiderless_optype(circ.get_OpType_from_Vertex(v_t)));
518
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 15 p_t = circ.get_target_port(next_e);
519 }
520
521 ZXVertPort zx_vp_s =
522
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 153 vert_lookup.at(TypedVertPort(VertPort(v_s, p_s), ZXPortType::Out));
523 ZXVertPort zx_vp_t =
524
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 153 vert_lookup.at(TypedVertPort(VertPort(v_t, p_t), ZXPortType::In));
525
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 153 if (circ.get_edgetype(edge) == EdgeType::Quantum) {
526
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 124 zxd.add_wire(
527 zx_vp_s.first, zx_vp_t.first, ZXWireType::Basic, QuantumType::Quantum,
528 zx_vp_s.second, zx_vp_t.second);
529 } else {
530
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 29 auto bool_it = boolean_outport_lookup.find(VertPort(v_s, p_s));
531
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 29 if (bool_it == boolean_outport_lookup.end()) {
532
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 12 zxd.add_wire(
533 zx_vp_s.first, zx_vp_t.first, ZXWireType::Basic,
534 QuantumType::Classical, zx_vp_s.second, zx_vp_t.second);
535 } else {
536 // If the source port is boolean, then connect the copy spider to the
537 // source vertex. All out-edges originated from the source port should
538 // be connected to the copy spider.
539
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 17 if (zxd.degree(bool_it->second.first) == 0) {
540 8 zxd.add_wire(
541
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 8 zx_vp_s.first, bool_it->second.first, ZXWireType::Basic,
542 8 QuantumType::Classical, zx_vp_s.second, bool_it->second.second);
543 }
544 17 zxd.add_wire(
545
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 17 bool_it->second.first, zx_vp_t.first, ZXWireType::Basic,
546 17 QuantumType::Classical, bool_it->second.second, zx_vp_t.second);
547 }
548 }
549 }
550 76 return bmap;
551 38 }
552
553 29 std::pair<ZXDiagram, BoundaryVertMap> circuit_to_zx(const Circuit& circ) {
554
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 29 ZXDiagram zxd;
555
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 29 BoundaryVertMap bmap = circuit_to_zx_recursive(circ, zxd, true);
556 // Remove internal boundary vertices produced by the recursion
557
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 29 ZXVertVec true_boundary = zxd.get_boundary();
558 29 ZXVertIterator vi, vi_end, next;
559
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 29 tie(vi, vi_end) = boost::vertices(*zxd.get_graph());
560
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 378 for (next = vi; vi != vi_end; vi = next) {
561 349 ++next;
562
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 349 if ((zxd.get_zxtype(*vi) == ZXType::Input ||
563
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 503 zxd.get_zxtype(*vi) == ZXType::Output) &&
564
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 154 std::find(true_boundary.begin(), true_boundary.end(), *vi) ==
565
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 503 true_boundary.end()) {
566
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 32 WireVec adj_wires = zxd.adj_wires(*vi);
567 TKET_ASSERT(adj_wires.size() == 2);
568 TKET_ASSERT(zxd.get_qtype(adj_wires[0]) == zxd.get_qtype(adj_wires[1]));
569
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 32 TKET_ASSERT(
570 zxd.get_wire_type(adj_wires[0]) == zxd.get_wire_type(adj_wires[1]));
571
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 32 ZXVertVec neighbours = zxd.neighbours(*vi);
572
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 128 zxd.add_wire(
573 64 neighbours[0], neighbours[1], zxd.get_wire_type(adj_wires[0]),
574 32 zxd.get_qtype(adj_wires[0]));
575
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 32 zxd.remove_vertex(*vi);
576 32 }
577 }
578
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 58 return {std::move(zxd), std::move(bmap)};
579 29 }
580
581 50 void clean_frontier(
582 ZXDiagram& diag, ZXVertVec& frontier, Circuit& circ,
583 std::map<ZXVert, unsigned>& qubit_map) {
584 50 std::set<ZXVert> frontier_lookup;
585 50 std::list<std::pair<ZXVert, ZXVert>> czs;
586
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 255 for (const ZXVert& f : frontier) {
587
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 205 frontier_lookup.insert(f);
588
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 836 for (const Wire& w : diag.adj_wires(f)) {
589
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 631 ZXVert n = diag.other_end(w, f);
590
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 631 if (diag.get_zxtype(n) == ZXType::Output) {
591
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 205 unsigned q = qubit_map.at(n);
592
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 205 if (diag.get_wire_type(w) == ZXWireType::H) {
593
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 48 diag.set_wire_type(w, ZXWireType::Basic);
594
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 48 circ.add_op<unsigned>(OpType::H, {q});
595 }
596
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 205 switch (diag.get_zxtype(f)) {
597
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 ✗ case ZXType::Input: {
598 ✗ break;
599 }
600
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 38 case ZXType::XY: {
601
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 38 const PhasedGen& f_gen = diag.get_vertex_ZXGen<PhasedGen>(f);
602
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 38 Expr ph = f_gen.get_param();
603
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 38 if (!equiv_0(ph)) {
604
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 21 circ.add_op<unsigned>(OpType::U1, -ph, {q});
605 }
606
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 38 diag.set_vertex_ZXGen_ptr(
607
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 76 f, ZXGen::create_gen(ZXType::PX, QuantumType::Quantum));
608 38 break;
609 38 }
610
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 167 case ZXType::PX: {
611
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 167 const CliffordGen& f_gen = diag.get_vertex_ZXGen<CliffordGen>(f);
612
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 167 if (f_gen.get_param()) {
613 ✗ circ.add_op<unsigned>(OpType::Z, {q});
614 ✗ diag.set_vertex_ZXGen_ptr(
615 ✗ f, ZXGen::create_gen(ZXType::PX, QuantumType::Quantum));
616 }
617 167 break;
618 }
619
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 ✗ case ZXType::PY: {
620 ✗ const CliffordGen& f_gen = diag.get_vertex_ZXGen<CliffordGen>(f);
621 ✗ circ.add_op<unsigned>(
622 ✗ f_gen.get_param() ? OpType::S : OpType::Sdg, {q});
623 ✗ diag.set_vertex_ZXGen_ptr(
624 ✗ f, ZXGen::create_gen(ZXType::PX, QuantumType::Quantum));
625 ✗ break;
626 }
627
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 ✗ default:
628 ✗ throw ZXError(
629 "Error during extraction from ZX diagram: unexpected ZXType in "
630 ✗ "frontier");
631 }
632
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 426 } else if (frontier_lookup.find(n) != frontier_lookup.end()) {
633
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 28 czs.push_back({f, n});
634
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 28 diag.remove_wire(w);
635 }
636 205 }
637 }
638
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 78 for (const std::pair<ZXVert, ZXVert>& pair : czs) {
639
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 56 circ.add_op<unsigned>(
640
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 28 OpType::CZ, {qubit_map.at(pair.first), qubit_map.at(pair.second)});
641 }
642 100 ZXVertVec new_frontier;
643
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 255 for (const ZXVert& f : frontier) {
644 205 bool removed = false;
645
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 205 ZXVertVec ns = diag.neighbours(f);
646
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 205 if (ns.size() == 2) {
647
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 96 ZXType nt0 = diag.get_zxtype(ns.at(0));
648
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 96 ZXType nt1 = diag.get_zxtype(ns.at(1));
649
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 96 if ((nt0 == ZXType::Input && nt1 == ZXType::Output) ||
650
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 69 (nt0 == ZXType::Output && nt1 == ZXType::Input)) {
651
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 8 diag.add_wire(ns.at(0), ns.at(1));
652
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 8 diag.remove_vertex(f);
653 8 removed = true;
654 }
655 }
656
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 205 if (!removed && diag.get_zxtype(f) != ZXType::Input)
657
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 197 new_frontier.push_back(f);
658 205 }
659
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 50 frontier = new_frontier;
660 50 }
661
662 38 ZXVertSeqSet neighbours_of_frontier(
663 const ZXDiagram& diag, const ZXVertVec& frontier) {
664 38 ZXVertSeqSet n_set;
665
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 185 for (const ZXVert& f : frontier) {
666
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 542 for (const Wire& w : diag.adj_wires(f)) {
667
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 395 ZXVert n = diag.other_end(w, f);
668
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 395 ZXType n_type = diag.get_zxtype(n);
669
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 395 if (n_type == ZXType::Output || n_type == ZXType::Input) continue;
670
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 248 n_set.insert(n);
671 147 }
672 }
673 38 return n_set;
674 }
675
676 50 static void bipartite_complementation(
677 ZXDiagram& diag, const ZXVertSeqSet& sa, const ZXVertSeqSet& sb) {
678
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 90 for (const ZXVert& a : sa.get<TagSeq>()) {
679
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 201 for (const ZXVert& b : sb.get<TagSeq>()) {
680
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 161 std::optional<Wire> wire = diag.wire_between(a, b);
681
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 161 if (wire)
682
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 78 diag.remove_wire(*wire);
683 else
684
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 83 diag.add_wire(a, b, ZXWireType::H);
685 }
686 }
687 50 }
688
689 100 void extend_if_input(
690 ZXDiagram& diag, const ZXVert& v, std::map<ZXVert, ZXVert>& input_qubits) {
691
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 100 std::map<ZXVert, ZXVert>::iterator found = input_qubits.find(v);
692
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 100 if (found != input_qubits.end()) {
693 5 ZXVert in = found->second;
694
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 5 ZXVert ext0 = diag.add_vertex(ZXType::XY);
695
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 5 ZXVert ext1 = diag.add_vertex(ZXType::XY);
696
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 5 diag.remove_wire(diag.adj_wires(in).at(0));
697
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 5 diag.add_wire(in, ext0);
698
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 5 diag.add_wire(ext0, ext1, ZXWireType::H);
699
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 5 diag.add_wire(ext1, v, ZXWireType::H);
700
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 5 input_qubits.erase(found);
701
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 5 input_qubits.insert({ext0, in});
702 }
703 100 }
704
705 38 bool remove_all_gadgets(
706 ZXDiagram& diag, const ZXVertVec& frontier,
707 std::map<ZXVert, ZXVert>& input_qubits) {
708 38 bool removed_gadget = false;
709
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 185 for (const ZXVert& f : frontier) {
710
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 147 ZXVertVec f_ns = diag.neighbours(f);
711 147 std::optional<ZXVert> found_output;
712
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 282 for (const ZXVert& n : f_ns) {
713 // Each frontier vertex is connected to a unique output, find it
714
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 282 if (diag.get_zxtype(n) == ZXType::Output) {
715 147 found_output = n;
716 147 break;
717 }
718 }
719
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 147 if (!found_output)
720 ✗ throw ZXError(
721 "Error during extraction from ZXDiagram: frontier vertex not "
722 ✗ "adjacent to an output");
723 147 ZXVert o = *found_output;
724
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 522 for (const ZXVert& n : f_ns) {
725
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 385 if (diag.get_zxtype(n) == ZXType::YZ) {
726 // Pivot
727 // Identify three subsets of neighbours
728
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 10 ZXVertSeqSet excl_f;
729 // Need to recalculate neighbours rather than use f_ns as we might have
730 // extended
731
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 10 extend_if_input(diag, f, input_qubits);
732
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 75 for (const ZXVert& n : diag.neighbours(f)) {
733
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 65 extend_if_input(diag, n, input_qubits);
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 65 excl_f.insert(n);
735 10 }
736
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 10 excl_f.get<TagKey>().erase(n);
737
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 10 excl_f.get<TagKey>().erase(o);
738
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 10 ZXVertSeqSet excl_n, joint;
739 10 auto& lookup_f = excl_f.get<TagKey>();
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 35 for (const ZXVert& nn : diag.neighbours(n)) {
741
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 25 extend_if_input(diag, nn, input_qubits);
742
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 25 if (lookup_f.find(nn) != lookup_f.end())
743
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 5 joint.insert(nn);
744 else
745
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 20 excl_n.insert(nn);
746 10 }
747
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 10 excl_n.get<TagKey>().erase(f);
748
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 15 for (const ZXVert& nn : joint.get<TagSeq>())
749
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 5 excl_f.get<TagKey>().erase(nn);
750 // The is_MBQC check in zx_to_circuit guarantees QuantumType::Quantum
751
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 10 bipartite_complementation(diag, joint, excl_n);
752
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 10 bipartite_complementation(diag, joint, excl_f);
753
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 10 bipartite_complementation(diag, excl_n, excl_f);
754 // In place of switching vertices f and n, we invert their
755 // connectivities
756
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 10 excl_n.insert(excl_f.begin(), excl_f.end());
757
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 10 bipartite_complementation(diag, {f}, excl_n);
758
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 10 bipartite_complementation(diag, {n}, excl_n);
759
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 10 Wire ow = *diag.wire_between(f, o);
760
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 10 diag.set_wire_type(
761
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 10 ow, (diag.get_wire_type(ow) == ZXWireType::Basic)
762 ? ZXWireType::H
763 : ZXWireType::Basic);
764
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 10 const PhasedGen& yz_gen = diag.get_vertex_ZXGen<PhasedGen>(n);
765
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 10 diag.set_vertex_ZXGen_ptr(
766
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 20 n, ZXGen::create_gen(
767
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 20 ZXType::XY, -yz_gen.get_param(), QuantumType::Quantum));
768
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 15 for (const ZXVert& nn : joint.get<TagSeq>()) {
769 5 ZXGen_ptr new_gen;
770
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 5 switch (diag.get_zxtype(nn)) {
771
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 5 case ZXType::XY: {
772
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 5 const PhasedGen& ph_gen = diag.get_vertex_ZXGen<PhasedGen>(nn);
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 10 new_gen = ZXGen::create_gen(
774
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 15 ZXType::XY, ph_gen.get_param() + 1., QuantumType::Quantum);
775 5 break;
776 }
777 ✗ case ZXType::PX:
778 case ZXType::PY: {
779 const CliffordGen& cl_gen =
780 ✗ diag.get_vertex_ZXGen<CliffordGen>(nn);
781 ✗ new_gen = ZXGen::create_gen(
782 ✗ cl_gen.get_type(), !cl_gen.get_param(), QuantumType::Quantum);
783 ✗ break;
784 }
785 ✗ case ZXType::XZ:
786 case ZXType::YZ: {
787 ✗ const PhasedGen& ph_gen = diag.get_vertex_ZXGen<PhasedGen>(nn);
788 ✗ new_gen = ZXGen::create_gen(
789 ✗ ph_gen.get_type(), -ph_gen.get_param(), QuantumType::Quantum);
790 ✗ break;
791 }
792
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 ✗ case ZXType::PZ: {
793 ✗ new_gen = diag.get_vertex_ZXGen_ptr(nn);
794 ✗ break;
795 }
796
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 ✗ default:
797 ✗ throw ZXError(
798 "Error during extraction from ZX diagram: unexpected ZXType "
799 ✗ "during local complementation");
800 }
801
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 5 diag.set_vertex_ZXGen_ptr(nn, new_gen);
802 5 }
803 10 removed_gadget = true;
804 10 break;
805 10 }
806 }
807 147 }
808 38 return removed_gadget;
809 }
810
811 2 Circuit zx_to_circuit(const ZXDiagram& d) {
812
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 2 ZXDiagram diag = d;
813
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 2 if (!diag.is_MBQC())
814 ✗ throw ZXError("Can only extract a circuit from a ZX diagram in MBQC form");
815
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 2 ZXVertVec ins = diag.get_boundary(ZXType::Input);
816
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 2 ZXVertVec outs = diag.get_boundary(ZXType::Output);
817
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 2 if (ins.size() != outs.size())
818 ✗ throw ZXError("Can only extract a circuit from a unitary ZX diagram");
819
820
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 2 Circuit circ(ins.size());
821
822 2 ZXVertVec frontier;
823 2 std::map<ZXVert, unsigned> qubit_map;
824 2 unsigned q = 0;
825
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 10 for (const ZXVert& o : outs) {
826
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 8 ZXVert f_i = diag.neighbours(o).at(0);
827
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 8 frontier.push_back(f_i);
828
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 8 qubit_map.insert({o, q});
829
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 8 qubit_map.insert({f_i, q});
830 8 ++q;
831 }
832 2 std::map<ZXVert, ZXVert> input_qubits;
833
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 10 for (const ZXVert& i : ins)
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 8 input_qubits.insert({diag.neighbours(i).at(0), i});
835
836
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 2 clean_frontier(diag, frontier, circ, qubit_map);
837
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 40 while (!frontier.empty()) {
838
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 38 if (remove_all_gadgets(diag, frontier, input_qubits)) {
839
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 10 clean_frontier(diag, frontier, circ, qubit_map);
840 }
841
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 38 ZXVertSeqSet neighbours = neighbours_of_frontier(diag, frontier);
842
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 114 boost::bimap<ZXVert, unsigned> correctors, preserve, ys;
843 38 ZXVertVec to_solve;
844
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 185 for (const ZXVert& f : frontier) {
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 147 if (input_qubits.find(f) == input_qubits.end())
846
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 147 correctors.insert({f, (unsigned)correctors.size()});
847 }
848
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 214 for (const ZXVert& n : neighbours.get<TagSeq>()) {
849
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 176 ZXType n_type = diag.get_zxtype(n);
850
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 176 if (n_type == ZXType::XY || n_type == ZXType::PX ||
851 n_type == ZXType::PY) {
852
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 176 preserve.insert({n, (unsigned)preserve.size()});
853
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 176 to_solve.push_back(n);
854 }
855 }
856 std::map<ZXVert, ZXVertSeqSet> candidates =
857
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 38 Flow::gauss_solve_correctors(diag, correctors, preserve, to_solve, ys);
858
859
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 38 if (candidates.empty())
860 ✗ throw ZXError(
861 "Error during extraction from ZX diagram: diagram does not have "
862 ✗ "gflow");
863
864 38 unsigned min = UINT_MAX;
865 ZXVert best;
866
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 147 for (const std::pair<const ZXVert, ZXVertSeqSet>& p : candidates) {
867
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 109 if (p.second.size() < min) {
868 51 min = p.second.size();
869 51 best = p.first;
870 }
871 }
872
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 38 ZXVertSeqSet g_best = candidates.at(best);
873
874
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 38 ZXVert f_to_isolate = g_best.get<TagSeq>().front();
875
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 38 unsigned f_q = qubit_map.at(f_to_isolate);
876
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 79 for (const ZXVert& f : g_best) {
877
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 41 if (f != f_to_isolate) {
878
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 3 circ.add_op<unsigned>(OpType::CX, {f_q, qubit_map.at(f)});
879 }
880 }
881 ZXVert out;
882
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 38 Wire w_out;
883
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 53 for (const Wire& w : diag.adj_wires(f_to_isolate)) {
884
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 53 ZXVert n = diag.other_end(w, f_to_isolate);
885
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 53 if (diag.get_zxtype(n) == ZXType::Output) {
886 38 out = n;
887 38 w_out = w;
888 38 break;
889 }
890 38 }
891
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 76 diag.add_wire(
892 best, out,
893
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 38 (diag.get_wire_type(w_out) == ZXWireType::Basic) ? ZXWireType::H
894 : ZXWireType::Basic);
895
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 38 diag.remove_vertex(f_to_isolate);
896
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 38 qubit_map.erase(qubit_map.find(f_to_isolate));
897
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 38 qubit_map.insert({best, f_q});
898
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 87 for (ZXVertVec::iterator it = frontier.begin(); it != frontier.end();
899 49 ++it) {
900
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 87 if (*it == f_to_isolate) {
901 38 *it = best;
902 38 break;
903 }
904 }
905
906
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 38 clean_frontier(diag, frontier, circ, qubit_map);
907 38 }
908
909 2 qubit_map_t qm;
910
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 10 for (unsigned i = 0; i < ins.size(); ++i) {
911
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 8 ZXVert in = ins.at(i);
912
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 8 ZXVert out = diag.neighbours(in).at(0);
913
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 8 if (diag.get_zxtype(out) != ZXType::Output)
914 ✗ throw ZXError(
915 "Error during extraction from ZX diagram: input not adjacent to "
916 ✗ "output after extracting");
917
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 8 qm.insert({Qubit(qubit_map.at(out)), Qubit(i)});
918 }
919
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 2 circ.permute_boundary_output(qm);
920
921 // Reverse gates in circuit (all gates added are self-transpose)
922
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 4 return circ.transpose();
923 2 }
924
925 } // namespace tket
926