GCC Code Coverage Report

Directory: ./
File: Circuit/macro_manipulation.cpp
Date: 2022-10-15 05:10:18
Exec Total Coverage
Lines: 442 478 92.5%
Functions: 25 25 100.0%
Branches: 590 1062 55.6%
Decisions: 7 18 38.9%
Line Branch Decision Exec Source
1 // Copyright 2019-2022 Cambridge Quantum Computing
2 //
3 // Licensed under the Apache License, Version 2.0 (the "License");
4 // you may not use this file except in compliance with the License.
5 // You may obtain a copy of the License at
6 //
7 // http://www.apache.org/licenses/LICENSE-2.0
8 //
9 // Unless required by applicable law or agreed to in writing, software
10 // distributed under the License is distributed on an "AS IS" BASIS,
11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12 // See the License for the specific language governing permissions and
13 // limitations under the License.
14
15 /////////////////////////////////////////////////////
16 // ALL METHODS TO PERFORM COMPLEX CIRCUIT MANIPULATION//
17 /////////////////////////////////////////////////////
18
19 #include <memory>
20 #include <tklog/TketLog.hpp>
21
22 #include "Circuit.hpp"
23 #include "Gate/Gate.hpp"
24 #include "Ops/ClassicalOps.hpp"
25 #include "Utils/UnitID.hpp"
26 namespace tket {
27
28 442892 vertex_map_t Circuit::copy_graph(
29 const Circuit& c2, BoundaryMerge boundary_merge,
30 OpGroupTransfer opgroup_transfer) {
31
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 442892 switch (opgroup_transfer) {
32
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 ✗ case OpGroupTransfer::Preserve:
33 // Fail if any collisions.
34
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 ✗ for (const auto& opgroupsig : c2.opgroupsigs) {
35
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 ✗ if (opgroupsigs.find(opgroupsig.first) != opgroupsigs.end()) {
36 ✗ throw CircuitInvalidity("Name collision in inserted circuit");
37 }
38 }
39 // Add inserted opgroups to circuit.
40 ✗ opgroupsigs.insert(c2.opgroupsigs.begin(), c2.opgroupsigs.end());
41 ✗ break;
42
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 222753 case OpGroupTransfer::Disallow:
43 // Fail if any opgroups.
44
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 222753 if (!c2.opgroupsigs.empty()) {
45 ✗ throw CircuitInvalidity("Named op groups in inserted circuit");
46 }
47 222753 break;
48
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 220139 case OpGroupTransfer::Merge:
49 // Fail if any mismatched signatures
50
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 220158 for (const auto& opgroupsig : c2.opgroupsigs) {
51
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 19 if (opgroupsigs.find(opgroupsig.first) != opgroupsigs.end()) {
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 11 if (opgroupsigs[opgroupsig.first] != opgroupsig.second) {
53 ✗ throw CircuitInvalidity(
54 ✗ "Name signature mismatch in inserted circuit");
55 }
56 }
57 }
58 // Add inserted opgroups to circuit.
59 220139 opgroupsigs.insert(c2.opgroupsigs.begin(), c2.opgroupsigs.end());
60 220139 break;
61
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 ✗ default:
62 TKET_ASSERT(opgroup_transfer == OpGroupTransfer::Remove);
63 // Ignore inserted opgroups
64 ✗ break;
65 }
66
67 442892 vertex_map_t isomap;
68
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 442892 if (&c2 == this) {
69 ✗ throw Unsupported(
70 "Circuit Cannot currently copy itself using this method. Use * "
71 ✗ "instead\n");
72 }
73
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 3355623 BGL_FORALL_VERTICES(v, c2.dag, DAG) {
74
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 2469870 Vertex v0 = boost::add_vertex(this->dag);
75
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 2469870 this->dag[v0].op = c2.get_Op_ptr_from_Vertex(v);
76
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 2469870 if (opgroup_transfer == OpGroupTransfer::Preserve ||
77 opgroup_transfer == OpGroupTransfer::Merge) {
78
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 1436974 this->dag[v0].opgroup = c2.get_opgroup_from_Vertex(v);
79 }
80
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 2469870 isomap.insert({v, v0});
81 }
82
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 3355623 BGL_FORALL_VERTICES(v, c2.dag, DAG) {
83
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 2469870 EdgeVec edges = c2.get_in_edges(v);
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 2469870 Vertex target_v = isomap.find(v)->second;
85
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 4577583 for (EdgeVec::iterator e1 = edges.begin(); e1 != edges.end(); ++e1) {
86
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 2107713 Vertex old_source_v = c2.source(*e1);
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 2107713 Vertex source_v = isomap.find(old_source_v)->second;
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 2107713 add_edge(
89
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 4215426 {source_v, get_source_port(*e1)}, {target_v, get_target_port(*e1)},
90
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 2107713 c2.dag[*e1].type);
91 }
92 2469870 }
93
94
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 442892 if (boundary_merge == BoundaryMerge::Yes) {
95
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 450355 for (const BoundaryElement& el : c2.boundary.get<TagID>()) {
96
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 270170 std::string reg_name = el.id_.reg_name();
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 270170 register_info_t reg_type = el.reg_info();
98
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 270170 opt_reg_info_t reg_found = get_reg_info(reg_name);
99
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 270170 if (reg_found) {
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 89409 if (reg_found.value() != reg_type) {
101 ✗ throw Unsupported(
102 "Cannot merge circuits with different types for "
103 ✗ "register with name: " +
104 ✗ reg_name);
105 }
106
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 89409 boundary_t::iterator unit_found = boundary.get<TagID>().find(el.id_);
107
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 89409 if (unit_found != boundary.get<TagID>().end()) {
108 ✗ throw Unsupported(
109 ✗ "Cannot merge circuits as both contain unit: " + el.id_.repr());
110 }
111 }
112
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 270170 Vertex new_in = isomap[el.in_];
113
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 270170 Vertex new_out = isomap[el.out_];
114
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 270170 boundary.insert({el.id_, new_in, new_out});
115 270170 }
116 }
117 442892 return isomap;
118 }
119
120 // given two circuits, adds second circuit to first circuit object in parallel
121 1 Circuit operator*(const Circuit& c1, const Circuit& c2) {
122 // preliminary method to add circuit objects together
123 1 Circuit new_circ;
124
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 1 new_circ.copy_graph(c1);
125
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 1 new_circ.copy_graph(c2);
126
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 1 new_circ.add_phase(c1.get_phase() + c2.get_phase());
127 1 return new_circ;
128 }
129
130
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 13974 void Circuit::append(const Circuit& c2) { append_with_map(c2, {}); }
131
132 // qm is from the units on the second (appended) circuit to the units on the
133 // first (this) circuit
134 39898 void Circuit::append_with_map(const Circuit& c2, const unit_map_t& qm) {
135
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 39898 Circuit copy = c2;
136
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 39898 copy.rename_units(qm);
137
138 // Check what we need to do at the joins:
139 // Output --- Input ==> -------------
140 // Output --- Create ==> --- Reset ---
141 // Discard --- Input ==> [not allowed]
142 // Discard --- Create ==> --- Reset ---
143
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 39896 qubit_vector_t qbs = copy.all_qubits();
144
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 39896 std::set<Qubit> qbs_set(qbs.begin(), qbs.end());
145 39896 std::set<Qubit> reset_qbs;
146
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 208530 for (auto qb : all_qubits()) {
147
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 168635 if (qbs_set.find(qb) != qbs_set.end()) {
148
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 85087 if (copy.is_created(qb)) {
149
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 3 reset_qbs.insert(qb);
150
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 85084 } else if (is_discarded(qb)) {
151
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 1 throw CircuitInvalidity("Cannot append input qubit to discarded qubit");
152 }
153 }
154 208531 }
155
156 // Copy c2 into c1 but do not merge boundaries
157
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 39895 vertex_map_t vm = copy_graph(copy, BoundaryMerge::No);
158
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 39895 const Op_ptr noop = get_op_ptr(OpType::noop);
159
160 // Connect each matching qubit and bit, merging remainder
161
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 125018 for (const BoundaryElement& el : copy.boundary.get<TagID>()) {
162
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 85123 std::string reg_name = el.reg_name();
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 85123 register_info_t reg_type = el.reg_info();
164
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 85123 opt_reg_info_t reg_found = get_reg_info(reg_name);
165
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 85123 if (reg_found) {
166
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 85118 if (reg_found.value() != reg_type) {
167 ✗ throw Unsupported(
168 "Cannot append circuits with different types for "
169 ✗ "register with name: " +
170 ✗ reg_name);
171 }
172
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 85118 boundary_t::iterator unit_found = boundary.get<TagID>().find(el.id_);
173
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 85118 if (unit_found != boundary.get<TagID>().end()) {
174
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 85089 Vertex out = unit_found->out_;
175
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 85089 Vertex in = vm[el.in_];
176 // Update map
177
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 85089 BoundaryElement new_elem = *unit_found;
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 85089 new_elem.out_ = vm[el.out_];
179
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 85089 boundary.replace(unit_found, new_elem);
180 // Tie together
181
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 85089 if (reg_type.first == UnitType::Qubit)
182
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 85084 add_edge({out, 0}, {in, 0}, EdgeType::Quantum);
183 else
184
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 5 add_edge({out, 0}, {in, 0}, EdgeType::Classical);
185
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 85089 dag[out].op = noop;
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 85089 dag[in].op = noop;
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 85089 remove_vertex(out, GraphRewiring::Yes, VertexDeletion::Yes);
188
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 170173 if (el.type() != UnitType::Qubit ||
189
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 170173 reset_qbs.find(Qubit(el.id_)) == reset_qbs.end()) {
190
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 85087 remove_vertex(in, GraphRewiring::Yes, VertexDeletion::Yes);
191 } else {
192
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 2 dag[in].op = std::make_shared<const Gate>(OpType::Reset);
193 }
194 85089 } else {
195
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 29 Vertex new_in = vm[el.in_];
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 29 Vertex new_out = vm[el.out_];
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 29 boundary.insert({el.id_, new_in, new_out});
198 }
199 } else {
200
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 5 Vertex new_in = vm[el.in_];
201
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 5 Vertex new_out = vm[el.out_];
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 5 boundary.insert({el.id_, new_in, new_out});
203 }
204 85123 }
205
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 39895 add_phase(c2.get_phase());
206 39901 }
207
208 198 void Circuit::append_qubits(
209 const Circuit& c2, const std::vector<unsigned>& qubits,
210 const std::vector<unsigned>& bits) {
211 198 unit_map_t qm;
212
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 1006 for (unsigned i = 0; i < qubits.size(); i++) {
213
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 808 qm.insert({Qubit(i), Qubit(qubits[i])});
214 }
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 203 for (unsigned i = 0; i < bits.size(); i++) {
216
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 5 qm.insert({Bit(i), Bit(bits[i])});
217 }
218
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 198 append_with_map(c2, qm);
219 198 }
220
221 // given two circuits, adds second circuit to first sequentially by tying qubits
222 // together and returns a copy of this (to prevent destruction of initial
223 // circuits)
224 415 Circuit operator>>(const Circuit& ci1, const Circuit& ci2) {
225 415 Circuit new_circ = ci1;
226
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 415 new_circ.append(ci2);
227 415 return new_circ;
228 }
229
230 // Important substitute method. Requires knowledge of the boundary to insert
231 // into, and the vertices inside which are to be removed when substitution is
232 // performed. Gives the option to isolate the removed vertices but not delete
233 // them.
234 222812 void Circuit::substitute(
235 const Circuit& to_insert, const Subcircuit& to_replace,
236 VertexDeletion vertex_deletion, OpGroupTransfer opgroup_transfer) {
237
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 222812 if (!to_insert.is_simple()) throw SimpleOnly();
238
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 445624 if (to_insert.n_qubits() != to_replace.q_in_hole.size() ||
239
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 222812 to_insert.n_bits() != to_replace.c_in_hole.size())
240 ✗ throw CircuitInvalidity("Subcircuit boundary mismatch to hole");
241
242
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 222812 vertex_map_t vm = copy_graph(to_insert, BoundaryMerge::No, opgroup_transfer);
243 222812 VertexList bin;
244 222812 EdgeSet ebin; // Needs to be a set since subcircuit to replace could be
245 // trivial, essentially rewiring on a cut
246 222812 std::map<Edge, Vertex> c_out_map;
247
248
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 222812 const Op_ptr noop = get_op_ptr(OpType::noop);
249
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 477743 for (unsigned i = 0; i < to_replace.q_in_hole.size(); i++) {
250 254931 Edge edge = to_replace.q_in_hole[i];
251
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 254931 Vertex pred_v = source(edge);
252
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 254931 port_t port1 = get_source_port(edge);
253
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 254931 ebin.insert(edge);
254
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 254931 Vertex inp = vm[to_insert.get_in(Qubit(i))];
255
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 254931 add_edge({pred_v, port1}, {inp, 0}, EdgeType::Quantum);
256
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 254931 dag[inp].op = noop;
257
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 254931 bin.push_back(inp);
258 }
259
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 477743 for (unsigned i = 0; i < to_replace.q_out_hole.size(); i++) {
260 254931 Edge edge = to_replace.q_out_hole[i];
261
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 254931 Vertex succ_v = target(edge);
262
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 254931 port_t port2 = get_target_port(edge);
263
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 254931 ebin.insert(edge);
264
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 254931 Vertex outp = vm[to_insert.get_out(Qubit(i))];
265
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 254931 add_edge({outp, 0}, {succ_v, port2}, EdgeType::Quantum);
266
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 254931 dag[outp].op = noop;
267
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 254931 bin.push_back(outp);
268 }
269
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 223266 for (unsigned i = 0; i < to_replace.c_in_hole.size(); i++) {
270 454 Edge edge = to_replace.c_in_hole[i];
271
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 454 Vertex pred_v = source(edge);
272
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 454 port_t port1 = get_source_port(edge);
273
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 454 ebin.insert(edge);
274
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 454 Vertex inp = vm[to_insert.get_in(Bit(i))];
275
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 454 add_edge({pred_v, port1}, {inp, 0}, EdgeType::Classical);
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 454 dag[inp].op = noop;
277
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 454 bin.push_back(inp);
278 }
279
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 223266 for (unsigned i = 0; i < to_replace.c_out_hole.size(); i++) {
280 454 Edge edge = to_replace.c_out_hole[i];
281
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 454 Vertex succ_v = target(edge);
282
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 454 port_t port2 = get_target_port(edge);
283
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 454 ebin.insert(edge);
284
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 454 Vertex outp = vm[to_insert.get_out(Bit(i))];
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 454 add_edge({outp, 0}, {succ_v, port2}, EdgeType::Classical);
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 454 dag[outp].op = noop;
287
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 454 bin.push_back(outp);
288
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 454 c_out_map.insert({edge, outp});
289 }
290
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 222814 for (const Edge& e : to_replace.b_future) {
291
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 2 Edge c_out = get_nth_out_edge(source(e), get_source_port(e));
292
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 2 Vertex outp = c_out_map[c_out];
293
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 2 add_edge({outp, 0}, {target(e), get_target_port(e)}, EdgeType::Boolean);
294
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 2 ebin.insert(e);
295 }
296
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 731338 for (const Edge& e : ebin) {
297
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 508526 remove_edge(e);
298 }
299 // automatically rewire these canned vertices
300
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 222812 remove_vertices(bin, GraphRewiring::Yes, VertexDeletion::Yes);
301
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 222812 remove_vertices(to_replace.verts, GraphRewiring::No, vertex_deletion);
302
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 222812 add_phase(to_insert.get_phase());
303 222812 }
304
305 115146 void Circuit::substitute(
306 const Circuit& to_insert, const Vertex& to_replace,
307 VertexDeletion vertex_deletion, OpGroupTransfer opgroup_transfer) {
308 Subcircuit sub = {
309
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 115146 get_in_edges_of_type(to_replace, EdgeType::Quantum),
310
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 230292 get_out_edges_of_type(to_replace, EdgeType::Quantum),
311
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 230292 get_in_edges_of_type(to_replace, EdgeType::Classical),
312
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 230292 get_out_edges_of_type(to_replace, EdgeType::Classical),
313
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 230292 get_out_edges_of_type(to_replace, EdgeType::Boolean),
314
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 230292 {to_replace}};
315
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 115146 substitute(to_insert, sub, vertex_deletion, opgroup_transfer);
316 115146 }
317
318 220 void Circuit::substitute_conditional(
319 Circuit to_insert, const Vertex& to_replace, VertexDeletion vertex_deletion,
320 OpGroupTransfer opgroup_transfer) {
321
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 220 Op_ptr op = get_Op_ptr_from_Vertex(to_replace);
322
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 220 if (op->get_type() != OpType::Conditional)
323 ✗ throw CircuitInvalidity(
324 ✗ "substitute_conditional called with an unconditional gate");
325 Subcircuit sub = {
326
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 220 get_in_edges_of_type(to_replace, EdgeType::Quantum),
327
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 440 get_out_edges_of_type(to_replace, EdgeType::Quantum),
328
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 440 get_in_edges_of_type(to_replace, EdgeType::Classical),
329
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 440 get_out_edges_of_type(to_replace, EdgeType::Classical),
330
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 440 get_out_edges_of_type(to_replace, EdgeType::Boolean),
331
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 440 {to_replace}};
332 220 const Conditional& cond = static_cast<const Conditional&>(*op);
333
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 220 unsigned width = cond.get_width();
334 // Conditions are first few args, so increase index of all others
335 220 bit_map_t rename_map;
336
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 222 for (unsigned i = 0; i < to_insert.n_bits(); ++i) {
337
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 2 rename_map[Bit(i)] = Bit(i + width);
338 }
339
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 220 to_insert.rename_units(rename_map);
340 // Extend subcircuit hole with space for condition bits
341
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 220 bit_vector_t cond_bits(width);
342 220 EdgeVec cond_sources;
343
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 631 for (unsigned i = 0; i < width; ++i) {
344
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 411 cond_bits[i] = Bit(i);
345
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 411 Edge read_in = get_nth_in_edge(to_replace, i);
346 Edge source_write =
347
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 411 get_nth_out_edge(source(read_in), get_source_port(read_in));
348
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 411 cond_sources.push_back(source_write);
349 }
350
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 440 sub.c_in_hole.insert(
351 220 sub.c_in_hole.begin(), cond_sources.begin(), cond_sources.end());
352
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 440 sub.c_out_hole.insert(
353 220 sub.c_out_hole.begin(), cond_sources.begin(), cond_sources.end());
354
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 220 to_insert = to_insert.conditional_circuit(cond_bits, cond.get_value());
355
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 220 substitute(to_insert, sub, vertex_deletion, opgroup_transfer);
356 220 }
357
358 // given the edges to be broken and new
359 // circuit, implants circuit into old circuit
360 192 void Circuit::cut_insert(
361 const Circuit& incirc, const EdgeVec& q_preds, const EdgeVec& c_preds,
362 const EdgeVec& b_future) {
363
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 192 Subcircuit sub = {q_preds, q_preds, c_preds, c_preds, b_future};
364
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 192 substitute(incirc, sub, VertexDeletion::No);
365 192 }
366
367 119 void Circuit::replace_SWAPs() {
368 119 VertexList bin;
369
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 4641 BGL_FORALL_VERTICES(v, dag, DAG) {
370
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 4403 if (get_Op_ptr_from_Vertex(v)->get_type() == OpType::SWAP) {
371 101 Vertex swap = v;
372
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 101 EdgeVec outs = get_all_out_edges(v);
373 101 Edge out1 = outs[0];
374
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 101 dag[out1].ports.first = 1;
375 101 Edge out2 = outs[1];
376
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 101 dag[out2].ports.first = 0;
377
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 101 remove_vertex(swap, GraphRewiring::Yes, VertexDeletion::No);
378
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 101 bin.push_back(swap);
379 101 }
380 }
381
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 119 remove_vertices(bin, GraphRewiring::No, VertexDeletion::Yes);
382 119 }
383
384 27 void Circuit::replace_implicit_wire_swap(
385 const Qubit first, const Qubit second) {
386
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 81 add_op<UnitID>(OpType::CX, {first, second});
387
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 81 add_op<UnitID>(OpType::CX, {second, first});
388
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 81 Vertex cxvertex = add_op<UnitID>(OpType::CX, {first, second});
389
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 27 EdgeVec outs = get_all_out_edges(cxvertex);
390 27 Edge out1 = outs[0];
391
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 27 dag[out1].ports.first = 1;
392 27 Edge out2 = outs[1];
393
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 27 dag[out2].ports.first = 0;
394 27 }
395
396 // helper functions for the dagger and transpose
397 41618 void Circuit::_handle_boundaries(Circuit& circ, vertex_map_t& vmap) const {
398 // Handle boundaries
399
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 89727 for (const BoundaryElement& el : this->boundary.get<TagID>()) {
400 Vertex new_in;
401 Vertex new_out;
402
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 48109 if (el.id_.type() == UnitType::Bit) {
403 ✗ tket_log()->warn(
404 "The circuit contains classical data for which the dagger/transpose "
405 "might not be defined.");
406 ✗ new_in = circ.add_vertex(OpType::ClInput);
407 ✗ new_out = circ.add_vertex(OpType::ClOutput);
408 } else {
409
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 48109 new_in = circ.add_vertex(OpType::Input);
410
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 48109 new_out = circ.add_vertex(OpType::Output);
411 }
412 48109 Vertex old_in = el.in_;
413 48109 Vertex old_out = el.out_;
414
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 48109 vmap[old_in] = new_out;
415
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 48109 vmap[old_out] = new_in;
416
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 48109 circ.boundary.insert({el.id_, new_in, new_out});
417 }
418 41618 }
419
420 41618 void Circuit::_handle_interior(
421 Circuit& circ, vertex_map_t& vmap, V_iterator& vi, V_iterator& vend,
422 ReverseType reverse_op) const {
423 // Handle interior
424
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 225354 for (std::tie(vi, vend) = boost::vertices(this->dag); vi != vend; vi++) {
425
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 183736 const Op_ptr op = get_Op_ptr_from_Vertex(*vi);
426
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 183736 OpDesc desc = op->get_desc();
427
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 183736 if (is_boundary_q_type(desc.type())) {
428 96218 continue;
429
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 87518 } else if ((desc.is_gate() || desc.is_box()) && !desc.is_oneway()) {
430 87518 Op_ptr op_type_ptr;
431
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 87518 switch (reverse_op) {
432 87317 case ReverseType::dagger: {
433
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 87317 op_type_ptr = op->dagger();
434 87317 break;
435 }
436 201 case ReverseType::transpose: {
437
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 201 op_type_ptr = op->transpose();
438 201 break;
439 }
440 ✗ default: {
441 ✗ throw std::logic_error(
442 ✗ "Error in the definition of the dagger or transpose.");
443 }
444 }
445
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 87518 Vertex v = circ.add_vertex(op_type_ptr);
446
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 87518 vmap[*vi] = v;
447 87518 } else {
448 ✗ throw CircuitInvalidity(
449 ✗ "Cannot dagger or transpose op: " + op->get_name());
450 }
451
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 279954 }
452 41618 }
453
454 41618 void Circuit::_handle_edges(
455 Circuit& circ, vertex_map_t& vmap, E_iterator& ei, E_iterator& eend) const {
456
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 184127 for (std::tie(ei, eend) = boost::edges(this->dag); ei != eend; ei++) {
457
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 142509 Vertex s = source(*ei);
458
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 142509 port_t sp = get_source_port(*ei);
459
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 142509 Vertex t = target(*ei);
460
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 142509 port_t tp = get_target_port(*ei);
461
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 142509 circ.add_edge({vmap[t], tp}, {vmap[s], sp}, get_edgetype(*ei));
462 }
463 41618 }
464
465 // returns Hermitian conjugate of circuit, ie its inverse
466 41610 Circuit Circuit::dagger() const {
467
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 41610 Circuit c;
468 41610 vertex_map_t vmap;
469
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 41610 _handle_boundaries(c, vmap);
470
471 41610 V_iterator vi, vend;
472 41610 ReverseType dagger = ReverseType::dagger;
473
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 41610 _handle_interior(c, vmap, vi, vend, dagger);
474
475
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 41610 E_iterator ei, eend;
476
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 41610 _handle_edges(c, vmap, ei, eend);
477
478
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 41610 c.add_phase(-get_phase());
479 83220 return c;
480 41610 }
481
482 // returns transpose of circuit
483 8 Circuit Circuit::transpose() const {
484
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 8 Circuit c;
485 8 vertex_map_t vmap;
486
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 8 _handle_boundaries(c, vmap);
487
488 8 V_iterator vi, vend;
489 8 ReverseType transpose = ReverseType::transpose;
490
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 8 _handle_interior(c, vmap, vi, vend, transpose);
491
492
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 8 E_iterator ei, eend;
493
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 8 _handle_edges(c, vmap, ei, eend);
494
495
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 8 c.add_phase(get_phase());
496 16 return c;
497 8 }
498
499 98 bool Circuit::substitute_all(const Circuit& to_insert, const Op_ptr op) {
500
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 98 if (!to_insert.is_simple()) throw SimpleOnly();
501
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 98 if (op->n_qubits() != to_insert.n_qubits())
502
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 1 throw CircuitInvalidity(
503 "Cannot substitute all on mismatching arity between Vertex "
504 2 "and inserted Circuit");
505 97 VertexVec to_replace;
506 97 VertexVec conditional_to_replace;
507
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 8396 BGL_FORALL_VERTICES(v, dag, DAG) {
508
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 8202 Op_ptr v_op = get_Op_ptr_from_Vertex(v);
509
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 8202 if (*v_op == *op)
510
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 109 to_replace.push_back(v);
511
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 8093 else if (v_op->get_type() == OpType::Conditional) {
512 67 const Conditional& cond = static_cast<const Conditional&>(*v_op);
513
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 67 if (*cond.get_op() == *op) conditional_to_replace.push_back(v);
514 }
515 8202 }
516
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 206 for (const Vertex& v : to_replace) {
517
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 109 substitute(to_insert, v, VertexDeletion::Yes);
518 }
519
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 132 for (const Vertex& v : conditional_to_replace) {
520
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 35 substitute_conditional(to_insert, v, VertexDeletion::Yes);
521 }
522
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 194 return !(to_replace.empty() && conditional_to_replace.empty());
523 97 }
524
525 3 bool Circuit::substitute_named(
526 const Circuit& to_insert, const std::string opname) {
527
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 3 if (!to_insert.is_simple()) throw SimpleOnly();
528
529 // Check that no op group names are in common
530
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 4 for (const auto& opgroupsig : to_insert.opgroupsigs) {
531
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 2 if (opgroupsigs.find(opgroupsig.first) != opgroupsigs.end()) {
532
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 1 throw CircuitInvalidity("Name collision in replacement circuit");
533 }
534 }
535
536 // Do nothing if opname not present
537
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 2 if (opgroupsigs.find(opname) == opgroupsigs.end()) {
538 ✗ return false;
539 }
540
541 // Check signatures match
542
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 2 op_signature_t sig = opgroupsigs[opname];
543
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 2 unsigned sig_n_q = std::count(sig.begin(), sig.end(), EdgeType::Quantum);
544
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 2 unsigned sig_n_c = std::count(sig.begin(), sig.end(), EdgeType::Classical);
545
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 2 unsigned sig_n_b = std::count(sig.begin(), sig.end(), EdgeType::Boolean);
546
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 2 if (to_insert.n_qubits() != sig_n_q || to_insert.n_bits() != sig_n_c ||
547 sig_n_b != 0) {
548
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 1 throw CircuitInvalidity("Signature mismatch");
549 }
550
551 1 VertexVec to_replace;
552
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 16 BGL_FORALL_VERTICES(v, dag, DAG) {
553
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 14 std::optional<std::string> v_opgroup = get_opgroup_from_Vertex(v);
554
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 14 if (v_opgroup && v_opgroup.value() == opname) {
555
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 3 to_replace.push_back(v);
556 }
557 14 }
558
559
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 4 for (const Vertex& v : to_replace) {
560
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 3 substitute(to_insert, v, VertexDeletion::Yes, OpGroupTransfer::Merge);
561 }
562
563 1 return !to_replace.empty();
564 2 }
565
566 4 bool Circuit::substitute_named(Op_ptr to_insert, const std::string opname) {
567 // Do nothing if opname not present
568
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 4 if (opgroupsigs.find(opname) == opgroupsigs.end()) {
569 1 return false;
570 }
571
572 // Check signatures match
573
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 3 op_signature_t sig = opgroupsigs[opname];
574
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 3 if (to_insert->get_signature() != sig) {
575
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 1 throw CircuitInvalidity("Signature mismatch");
576 }
577
578 2 VertexVec to_replace;
579
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 35 BGL_FORALL_VERTICES(v, dag, DAG) {
580
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 31 std::optional<std::string> v_opgroup = get_opgroup_from_Vertex(v);
581
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 31 if (v_opgroup && v_opgroup.value() == opname) {
582
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 6 to_replace.push_back(v);
583 }
584 31 }
585
586
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 2 unsigned sig_n_q = std::count(sig.begin(), sig.end(), EdgeType::Quantum);
587
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 2 unsigned sig_n_c = std::count(sig.begin(), sig.end(), EdgeType::Classical);
588
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 2 Circuit c(sig_n_q, sig_n_c);
589
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 2 unit_vector_t args(sig_n_q + sig_n_c);
590
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 4 for (unsigned i = 0; i < sig_n_q; i++) args[i] = Qubit(i);
591
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 2 for (unsigned i = 0; i < sig_n_c; i++) args[sig_n_q + i] = Bit(i);
592
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 2 c.add_op(to_insert, args, opname);
593
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 8 for (const Vertex& v : to_replace) {
594
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 6 substitute(c, v, VertexDeletion::Yes, OpGroupTransfer::Merge);
595 }
596
597 2 return !to_replace.empty();
598 3 }
599
600 223 Circuit Circuit::conditional_circuit(
601 const bit_vector_t& bits, unsigned value) const {
602
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 223 if (has_implicit_wireswaps()) {
603
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 1 throw CircuitInvalidity("Cannot add conditions to an implicit wireswap");
604 }
605
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 444 Circuit cond_circ(all_qubits(), all_bits());
606
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 636 for (const Bit& b : bits) {
607
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 415 if (contains_unit(b)) {
608
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 3 Vertex in = get_in(b);
609
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 3 Vertex out = get_out(b);
610
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 3 if (get_successors_of_type(in, EdgeType::Classical).front() != out) {
611
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 1 throw CircuitInvalidity(
612 "Cannot add condition. Circuit has non-trivial "
613
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 2 "actions on bit " +
614
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 2 b.repr());
615 }
616 } else {
617
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 412 cond_circ.add_bit(b);
618 }
619 }
620 221 unsigned width = bits.size();
621
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 738 for (const Command& com : *this) {
622 517 const Op_ptr op = com.get_op_ptr();
623
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 517 Op_ptr cond_op = std::make_shared<Conditional>(op, width, value);
624
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 517 unit_vector_t args = com.get_args();
625
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 517 args.insert(args.begin(), bits.begin(), bits.end());
626
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 517 cond_circ.add_op(cond_op, args);
627 738 }
628
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 221 cond_circ.add_phase(get_phase());
629 442 return cond_circ;
630 1 }
631
632 4394 bool Circuit::substitute_box_vertex(
633 Vertex& vert, VertexDeletion vertex_deletion) {
634
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 4394 Op_ptr op = get_Op_ptr_from_Vertex(vert);
635 4394 bool conditional = op->get_type() == OpType::Conditional;
636
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 4394 if (conditional) {
637 9 const Conditional& cond = static_cast<const Conditional&>(*op);
638
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 9 op = cond.get_op();
639 }
640
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 4394 if (!op->get_desc().is_box()) return false;
641
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 47 if (op->get_type() == OpType::ClassicalExpBox) return false;
642 47 const Box& b = static_cast<const Box&>(*op);
643
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 47 Circuit replacement = *b.to_circuit();
644
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 47 if (conditional) {
645
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 3 substitute_conditional(
646 replacement, vert, vertex_deletion, OpGroupTransfer::Merge);
647 } else {
648
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 44 substitute(replacement, vert, vertex_deletion, OpGroupTransfer::Merge);
649 }
650 47 return true;
651 4394 }
652
653 57 bool Circuit::decompose_boxes() {
654 57 bool success = false;
655 57 VertexList bin;
656
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 4503 BGL_FORALL_VERTICES(v, dag, DAG) {
657
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 4389 if (substitute_box_vertex(v, VertexDeletion::No)) {
658
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 42 bin.push_back(v);
659 42 success = true;
660 }
661 }
662
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 57 remove_vertices(bin, GraphRewiring::No, VertexDeletion::Yes);
663 57 return success;
664 57 }
665
666 33 void Circuit::decompose_boxes_recursively() {
667
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 45 while (decompose_boxes()) {
668 }
669 33 }
670
671 4 std::map<Bit, bool> Circuit::classical_eval(
672 const std::map<Bit, bool>& values) const {
673 4 std::map<Bit, bool> v(values);
674
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 12 for (CommandIterator it = begin(); it != end(); ++it) {
675 8 Op_ptr op = it->get_op_ptr();
676 8 OpType optype = op->get_type();
677
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 8 if (!is_classical_type(optype)) {
678 ✗ throw CircuitInvalidity("Non-classical operation");
679 }
680 std::shared_ptr<const ClassicalEvalOp> cop =
681 8 std::dynamic_pointer_cast<const ClassicalEvalOp>(op);
682
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 8 unit_vector_t args = it->get_args();
683 8 unsigned n_args = args.size();
684
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 8 switch (optype) {
685 4 case OpType::ClassicalTransform: {
686
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 4 std::vector<bool> input(n_args);
687
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 12 for (unsigned i = 0; i < n_args; i++) {
688
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 8 input[i] = v[Bit(args[i])];
689 }
690
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 4 std::vector<bool> output = cop->eval(input);
691 TKET_ASSERT(output.size() == n_args);
692
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 12 for (unsigned i = 0; i < n_args; i++) {
693
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 8 v[Bit(args[i])] = output[i];
694 }
695 4 break;
696 4 }
697 4 case OpType::SetBits: {
698
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 4 std::vector<bool> output = cop->eval({});
699 TKET_ASSERT(output.size() == n_args);
700
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 8 for (unsigned i = 0; i < n_args; i++) {
701
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 4 v[Bit(args[i])] = output[i];
702 }
703 4 break;
704 4 }
705 ✗ default:
706 ✗ throw CircuitInvalidity("Unexpected operation in circuit");
707 }
708 12 }
709 4 return v;
710 }
711
712 } // namespace tket
713